Implementation Of 2d Convolution Algorithm On FPGA For Image Processing Application
Image processing is a growing field with tremendous potential and scope for development. With the advent of
advanced visual technologies, there is a need to have an ultra high speed processing machines to match the quality of the
high definition domain. The high end DSPs have drawbacks and limitations which can be addressed by implementing a
processing unit as a hardware design. An optimum architecture can be developed by prototyping it on Field Programmable
Gate Arrays. An ideal hardware architecture can be designed according to the specific requirement which can outperform the
more generic processors.
Keywords— Convolution, FPGA, Image processing, Pipelining.