Reconfigurable SPI Driver For MIPS Soft-Core Processor Using FPGA
Field Programmable Gate Arrays (FPGA) are used widely in applications which require high speed parallel
computing. It provides a perfect solution which requires short time for customization after manufacturing. MIPS soft-core
processor and SPI protocol soft-core implementation is well known in FPGA, but the customized driver for SPI
communication is not available. The SPI communication protocol is widely used in a wide range of devices such as sensors,
memory devices, I/O expanders, etc. The objective of this research is to design and test a reconfigurable SPI driver for MIPS
processor so that communication between devices which use an SPI protocol becomes feasible. Design requires three blocks
a soft-core MIPS processor, SPI protocol block and an interconnecting block between MIPS processor and SPI block. MIPS
processor loads the transmitting data and configuration bits in the SFR register of Data memory and SPI block reads that
register and after communication loads the received data into another SFR register which MIPS processor can read upon
request. To demonstrate the proposed technique, we wrote the code and verified the results. The design architecture is coded
using Verilog and VHDL based on top-down hierarchical design methodology and realized in Spartan-3E FPGA using
Xilinx ISE 14.7. Based on the ISE and FPGA implementation results, the maximum operating frequency of the whole
system is found to be 122.632 MHz.
Keywords- FPGA, MIPS, SPI, Verilog, VHDL,Reconfigrable Driver, SFR.