Paper Title
Comparison Of Single Precision Floating Point Multiplier Using Different Multiplier Algorithms
Abstract
This paper contains design of a single precision floating point multiplier by using different 24X24 bit multiplier
and then comparing the different floating point multiplier for the various performance parameters. The multipliers included
in this comparison are array multiplier, radix 4 booth multiplier, wallace tree multiplier and vedic multiplier. The designs
are modeled in Verilog HDL and synthesized based on the TSMC 180nm standard cell library. Comparisons are based on the
synthesis result obtained by synthesizing all the multiplier using Cadence Encounter RTL Compiler .
Keywords :Floating Point , Floating Point Multiplier