Paper Title
Feature Optimization Techniques in Image Classification: A Review

With the progression in deep submicron static CMOS design, small and handy electronic devices are design with low supply voltage and lower power dissipation. The area and power dissipation is the major concern for small devices to scale down with a burst-mode type integrated circuits. In this paper a method to diminish dynamic power, leakage and region of application-specified integrated circuits, without sacrificing performance. A dynamic CMOS design with stack transistor, High Threshold Leakage Control Transistor, TG-Based Technique, Supply voltage scaling, Sleep Transistor methods be discuss. These methods are use to diminish the static and dynamic power dissipation among the CMOS logic design with some area and delay tradeoffs. Keywords - CMOS, TG- Based Technique, Leakage, High Threshold