Optimisation of Network Processor Microarchitecture
With the advent of the Internet and with increasing connectivity across the globe, rapid growth is occurring in the
field of microprocessor technology, specifically in the area of computer networks, to keep up with the workload performed
by network nodes. This marks the rise of Network on Chip(NoC), which combines several tasks on a single chip, thus aptly
being named a Network Processor. Since this chip is entirely programmable, its applications are wide-ranging: from
encapsulation and de capsulation of packets to its use in intrusion detection systems.
This paper offers an understanding of the micro architecture of network processors in use today and offers a comprehensive
solution to optimize each operating module located on the chip. Specific emphasis is given to aspects that hold the pivotal key
to unlock low latency and improved data streaming throughput capability, thereby providing a much higher, desired
performance capable of alleviating the problems that the processor industry faces today. The paper also highlights the
importance of Network Processors for use in the Networks industry.
Keywords - Network Processor, Micro architecture, Network on Chip, Packet Processor, Latency, Throughput