Paper Title
Fault Tolerance Improvement of The Secured Circuits

One of the major problems in testing a system-on-chip is dealing with the optimal choice of the test sequence. In this paper, we propose an efficient test sequence for TMR secure circuits. The test sequence is a high level method based on three pulsations. An extension to the sequence with one pulsation is proposed and by simulation results its effectiveness in achieving a higher fault tolerance interval is demonstrated.