Paper Title
Design of a Low Power CMOS Image Sensor with a Hybrid Correlated Double Sampling for Mobile Sensor Networks

A low power CMOS Image Sensor(CIS) has a great role to implement mobile sensor networks. In this paper, a low power CIS with a hybrid Correlated Double Sampling (CDS) scheme is discussed. In order to improve the CIS performance, a mixed mode scheme composed of both an analog CDS and a digital CDS is proposed. With the technique, we can drastically reduce both the column Fixed Pattern Noise (FPN) and the power consumption. The prototype sensor was fabricated with a TowerJazz 0.18μm CIS technology and the pixel pitch is 2.2μm. The measured column FPN is 0.10 LSB and the power consumption is only 10mW at the 2.8V power supply voltage with 176x144 pixels Keywords - Low power CMOS Image Sensor, mobile sensor network, hybrid correlated doubling sampling, column fixed pattern noise