Delay Optimization of Concatenation and Incrementation Carry Skip Adder
The architecture of a 32-bit Carry Skip Adder to achieve less area, less power consumption, less delay
is presented in this paper. Totally two architectures are explained in this paper. In Conv-CSKA, 2:1 MUXs are
used in the skip logic in between the RCA stages to skip the carry. This 2:1 MUX requires 12 transistors to
implement in CMOS level which occupies large amount of area which in turn increases the power consumption.
So, in CI-CSKA these 2:1 MUX are replaced with AOI,OAI logic to implement the skip logic technique and they
require only 6 transistors to implement. So, area, power, delay are reduced to 50% when compared with
Conv-CSKA. In addition, in case of CI-CSKA, except for the first stage, all the inputs for the RCAs are zero hence
the name concatenation. So, there is no need for all the RCAs to wait for the input carry. Finally the comparison
results reveal that there is 50%decrement in the power consumption, area and delay of the proposed structure
when compared with the Conv-CSKA.
Index Terms - 32-bit Carry Skip Adder ,less delay ,2:1 MUX, AOI, OAI logic ,CI-CSKA.