Design and Implementation of High Speed and Energy Efficient Digital Circuit using Adaptive Logic
Timing-error-detection (TED)-based systems have been shown to reduce power consumption or increase yield due
to reduced margins. Reducing voltage in the circuit results in slow operation that incurs more delay. Canary circuits have been
designed for error detection and error correction approach. Canary circuit results in large delay. Adaptive logic has been
designed with dual latch phase in each stage. A combination of XNOR gate and flip-flop around each stage is added for the
verification of correct operation. The entire architecture was modeled using Verilog code with the help of XILINX ISE tool .
Index Terms - Timing margin, TED (Timing Error Detection), TEP (Timing Error Prevention), canary circuit.