VLSI M.A.O Architecture for High Efficiency Image Coding
A network-on-chip (NoC) improves the technology and the power dissipated starts to opposed with by the
additional elements of the correspond ion subsystem. Sample M.A.O architecture has been acquired as a new in-loop
filtering block in proposed system. To get the optimum A.O [aging offset] parameters exhaustive operations are required
because of the huge amount of samples. In this work, VLSI M.A.O architecture is implemented for the parameter estimation
for images to transmit in low data. In the proposed system the image is converted in to binary data, the row orig data is zero
padded if required and then M.A.O architecture operation with efficient data is produced. The total design is implemented
using both MATLAB and xilinx 14.7.
Keywords - M.A.O architecture, Aging offset [A.O], network-on-chip (NoC).