International Journal of Electrical, Electronics and Data Communication (IJEEDC)
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Statistics report
Aug. 2022
Submitted Papers : 80
Accepted Papers : 10
Rejected Papers : 70
Acc. Perc : 12%
Issue Published : 114
Paper Published : 1562
No. of Authors : 4260
  Journal Paper


Paper Title :
Low Power Mirror Sequence March Test Algorithm For Static Random Access Memories

Author :G Rajesh Kumar, K Babulu

Article Citation :G Rajesh Kumar ,K Babulu , (2014 ) " Low Power Mirror Sequence March Test Algorithm For Static Random Access Memories " , International Journal of Electrical, Electronics and Data Communication (IJEEDC) , pp. 06-10, Volume-2,Issue-5

Abstract : Abstract— Low power design has emerged as the most essential field of work in VLSI system design. At the same time power dissipation in testing became more critical while designing a testable integrated circuit. During testing the design will consume much more power compared with normal functional mode. A novel Static Random Access Memory Testing scheme is presented in this paper, which can test memories using March test algorithms with a great reduction in test power. Testing in March algorithms is done marching from top to bottom and from bottom to top in a sequential manner. Like this each byte in the memory is tested multiple number of times. Sequencing in these testing algorithms is of binary sequencing. Because of the binary sequencing multiple number of bits toggle in each address sequence. If the binary sequencing is replaced with Single bit change address sequencing, number of transitions in the sequence reduces. There by power consumption in the testing reduces enormously. March Y based Built in Self-Test (BIST) algorithm is described using Verilog HDL language and is simulated using Xilinx ISE. Spartan-3E FPGA is used to implement the architecture.

Type : Research paper

Published : Volume-2,Issue-5


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